New PDF release: 9th International Conference on Robotic, Vision, Signal

By Haidi Ibrahim, Shahid Iqbal, Soo Siang Teoh, Mohd Tafir Mustaffa

ISBN-10: 9811017190

ISBN-13: 9789811017193

ISBN-10: 9811017212

ISBN-13: 9789811017216

The continuing is a set of analysis papers offered, on the ninth foreign convention on Robotics, imaginative and prescient, sign Processing & energy purposes (ROVISP 2016), by means of researchers, scientists, engineers, academicians in addition to commercial execs from everywhere in the globe to provide their examine effects and improvement actions for oral or poster displays. the themes of curiosity are as follows yet usually are not restricted to:

• Robotics, keep an eye on, Mechatronics and Automation
• imaginative and prescient, picture, and sign Processing
• synthetic Intelligence and computing device Applications
• digital layout and functions
• Telecommunication platforms and Applications
• strength procedure and commercial Applications
• Engineering schooling

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Extra info for 9th International Conference on Robotic, Vision, Signal Processing and Power Applications: Empowering Research and Innovation

Example text

2 DTTS Comparator Design Figure 2 shows the comparator schematic with DTTS technique. The DTTS is a technique that has both the benefits of Multi Threshold CMOS (MTCMOS) and stack transistor [4, 6]. DTTS is chosen because of its capability of reducing the leakage power and also giving less impact on the propagation delay of the comparator. The sleep transistor is built with high threshold voltage with reduced in size which is turned off during inactive state. The transistor is designed as high threshold voltage by increasing the body effect.

Finally Sect. 4 concludes this work. 1 Conventional and Reduced VDD Comparator Figure 1 shows the schematic of conventional circuit that has been used and re-designed in this study. This conventional comparator circuit is chosen as it gives a high speed and moderate power consumption. Furthermore, the conventional comparator circuit can be also optimized easily due to its simple architecture. The circuit has two stages with an output inverter. The first stage is NMOS differential pair (NM0 and NM1) which is driven by tail current transistor NM2.

The comparator with MTSCStack technique shows the huge improvement in static power consumption compared to other techniques. This is because the entire transistor is turned off except transistor NM7 and PM7 to retain the logic state of the comparator. 2 % in static power consumption. On the other hand, the percentage of static power reduction of comparator with MTSCStack techniques shows significant result compared to comparator with reduced VDD and comparator with DTTS. The layout drawn is shown in Fig.

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9th International Conference on Robotic, Vision, Signal Processing and Power Applications: Empowering Research and Innovation by Haidi Ibrahim, Shahid Iqbal, Soo Siang Teoh, Mohd Tafir Mustaffa


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